The invention relates to a communications circuit including a multi-stream associative memory architecture usable in high-speed computer telephony applications.
Computer telephony is based on digital communication across time division multiplexed serial data lines, known as xe2x80x9cstreams.xe2x80x9d A typical computer telephony bus provides 16 or more streams, which each have between 32 and 128 time slots. A computer telephony switch creates connections between two time slots in two streams by moving data from an input time slot to an output time slot.
It is known to use a Content Addressable Memory (CAM) to manage connections in telephony switches. As the number of streams and time slots increases, however, the access time of the CAM needs to decrease in order for the CAM to be able to switch these signals. For example, in larger systems of 32 streams with 128 time slots each, a switch must compare the address field and access the data in a total of 30.5 nanoseconds, which is a relatively short time given today""s technology.
In one general aspect, the invention features a communications circuit that includes a first content-addressable memory block that has an address input, a plurality of physical locations each of which comprises an address field responsive to the address input and an output field, and an output responsive to the output fields. The circuit also has a second content-addressable memory block that has an address input, a plurality of physical locations each of which comprises an address field responsive to the address input and an output field, and an output responsive to the output fields. The circuit also includes a data memory having an address input responsive to the output of the first content-addressable memory block and to the output of the second content-addressable memory block.
In preferred embodiments, a first pipeline memory block is operatively connected between the output of the first content-addressable memory block and the address input of the data memory, and a second pipeline memory block is operatively connected between the output of the second content-addressable memory block and the address input of the data memory. The circuit can also include a second data memory having an address input responsive to the output of the first content-addressable memory block, and the second data memory can be unresponsive to the output of the second content-addressable memory block. The content-addressable memory blocks can have slower access times than do the data memories. A counter can have an output operatively connected to the address inputs of the first and second content-addressable memory blocks. The circuit can further include time division multiplexed communications interface circuitry operatively connected to the content-addressable memory blocks for switching time division multiplexed time slot data from a first plurality of data streams onto a second plurality of data streams using the content-addressable memory blocks. The time division multiplexed communications interface circuitry can be operable to access the first content-addressable memory block to service connections with a first stream and to access the second content-addressable memory block to service connections with a second stream. The time division multiplexed communications interface circuitry can be operable to simultaneously access the first and second content-addressable memory blocks to simultaneously service connections with first and second streams.
In another general aspect, the invention features a communications circuit that includes means for providing a first address to a first address input of a first content-addressable memory block, means for retrieving a first tag corresponding to the first address, and means for accessing a first data item in a first data memory at a first location pointed to by the first tag. The circuit also includes means for providing a second address to a second address input of a second content-addressable memory block, means for retrieving a second tag corresponding to the second address, and means for accessing a second data item in the first data memory at a second location pointed to by the second tag.
In preferred embodiments, the circuit includes means for pipelining the first and second tags. The means for providing, retrieving, and accessing can be part of means for switching time division multiplexed communications data streams. The means for providing a first address can be for providing to the first content-addressable memory block data from a first of the streams, and the means for providing a second address can be for providing to the second content-addressable memory block data from a second of the streams. The means for providing a first address and the means for providing a second address can be for respectively simultaneously providing data from a first of the streams to the first content-addressable memory block, and data from a second of the streams to the second content-addressable memory block.
In another general aspect, the invention features simultaneously providing a first address to a first address input of a first content-addressable memory block and providing a second address to a second address input of a second content-addressable memory block, retrieving a first tag corresponding to the first address in response to the step of providing a first address, retrieving a second tag corresponding to the second address in response to the step of providing a second address, accessing a first data item in a data memory at a first location pointed to by the first tag, and accessing a second data item in the data memory at a second location pointed to by the second tag.
In preferred embodiments, the first and second tags are pipelined. The steps of providing, retrieving, and accessing can be performed as part of a step of switching time division multiplexed communications data streams. The method can also include further sets of steps of providing, retrieving and accessing, and the sets of steps of providing and retrieving can be applied to the first content-addressable memory block for a first of the streams and to the second content-addressable memory block for a second of the streams. The steps of providing can simultaneously provide the first address from a first stream to the first content-addressable memory block and the second address from a second stream to the second content-addressable memory block.
Systems according to the invention can be advantageous because they may not be limited by the number of streams, the number of time slots, by technology, and/or may be scalable for larger or smaller computer telephony systems applications. Aspects of the invention also allow for hard-wired access restrictions.